Text Box: PCI       Peripheral Control Interconnect Intel led development of the PCI in the early 90’s to overcome the limitations of the original PC bus developed by IBM for the original IBM PC in 1986.  PCI won out over several evolving / competing efforts:    (bits@MHz)   ISA, Industry Standard Architecture, by IBM, originally (8@4) expanded to (16@8) for the 80286-based IBM AT (Advanced Technology). MCA,  MicroChannel Architecture, developed by IBM for the 1987 PS/2 architecture (32@10). EISA,  Extended ISA, led by Compaq with “Gang of 9” PC manufacturers, doubled the 16-bit AT ISA bus  (32@8) VESA,  Video Electronics Standards Association, a consortium of video graphics adapter developers, provided a more direct interface to the faster Local memory bus, resulting in VESA Local or VL (32@33)   pciC,  PCI-Conventional, debuted in 1993, along with Windows NT 3.0.  From the initial (32@33) spec various iterations evolved, guided by the Special Interest Group http://www.pcisig.com/home until, again, demand for video graphics performance led to a new local bus AGP, Advanced Graphics Protocol.  AGP 1x evolved to the current ceiling AGP 8x, now raised by pciE.   Following, is a table indicating growing performance through evolution of the Conventional PCI bus into what is termed the PCI eXtended, pciX, which has peaked at 1GB/s.  (b = bit; B = Byte)                                 The last line of this table is represented as PCI in the chart below depicting progress up to the pciE. 

Text Box: The source for graphics here provided may not  be accessible but is provided for proper credit to Intel:  http://www.intel.com/cd/channel/reseller/asmo-na/eng/tech_reference/tech_whitepapers/66919.htm   pci Express The new architecture, pciE, borrows from the model of network switches overcoming limitations of the hub interface to the shared Ethernet bus.  Just as switching resolves contention to Ethernet bus, the pciE switch transfers pciC addresses and driver calls transparently over a scalable, asynchronous, routing pathway (4 conductors) connecting computing endpoints (video, USB, etc) to the “host bridge” between processor and memory.   Each interconnect or route comprises 2 lanes, for full duplex send and receive transmissions.  Each lane is based on 2 conductors, which together transmit either data value 0 or 1, corresponding to the difference between the voltage of each conductor (differential).  This differential method is more immune to noise and so is scalable to higher data rates.  Initial implementation provides for throughput of 2.5Gb/sec per lane (direction), or 5Gb/s per route (full duplex) = .5GB/s = x1.   Thus pciE implements on the computer what the iNternet implements globally.  Asynchronous communication, one packet at a time, point-to-point, based on 32-bit or 64-bit addressing.  The existing 3 computer address spaces — memory, i/o, and configuration — are supplemented with a new space for Messaging, providing for all other house-keeping communications occurring beneath, and supporting, the operating system.   While this assures compatibility with prior operating systems, there is also provision for new capabilities tapped by new operating systems.   So raising the ceiling on the AGP 8x involves implementation of a single interface pciE-x16, with 16 lanes.   back to NCAD Workstations.

Bits

MHz

Mb/sec

MB/sec

32

33

1056

132

32

66

2112

264

64

66

4224

528

64

100

6400

800

64

133

8512

1064